1. Field of the Invention
The present invention relates to the mounting, encapsulation and thermal management of silicon chips.
2. Related Art
The mounting and encapsulation of semiconductor chips are the final steps in the process of manufacturing semiconductor chips. The thermal management of semiconductor chips has presented many problems in the mounting and encapsulation processes. The increasing amounts of heat generated by chips of newer design are constantly challenging the present technology to develop new materials and semiconductor package configurations designed to transfer heat more efficiently.
The internal mounting location and configuration of the chip package are extremely important in designing thermally efficient packages.
A standard technique for mounting silicon chips in semiconductor packages is to attach the chip to an alumina ceramic plate. This is sometimes done by depositing a layer of gold on the underside of the chip and on the top of the alumina ceramic plate and pressing the chip to the ceramic plate with heat. This procedure produces a low melting point gold-silicon eutectic which welds the chip to the ceramic. The alumina plate may have a raised rim, for the attachment of wire interconnections and a lid. However, the routine attachment of the chip to an internal substrate creates a thermal barrier which heat must pass through to be dissipated.
The two most significant modes of heat transfer in this context are heat conduction and heat convection. Heat conduction is the transfer of heat through a medium. Heat convection is the transfer of heat away from a hot body to an ambient mass of cooler fluid, e.g. air, generally having a constant temperature. The object in designing chip packages is to take advantage of materials with high thermal conductive properties and arrange them in configurations which best utilize heat conduction and heat convection to transfer heat away from the chip.
If the chip is likely to produce a large amount of heat, a means of efficient heat dissipation must be thermally coupled to it. The manner in which this is done depends largely upon the conditions under which the chip is to be used.
If the chip is to be used in relative isolation, then a heatsink may be attached to the opposing side of the alumina ceramic plate by an epoxy resin. The heatsink is typically aluminum and is configured with heat dissipating elements, such as fins, posts or the like, for greater surface area. The heat dissipating elements often take the form of a stack of circular fins joined together at their centers effectively forming a central rod. Heat passes from the alumina substrate, by conduction, into the heatsink and then is convected away over the surface area of the heat dissipating elements of the heatsink. Utilizing an epoxy bonded, external heatsink is effective with low power chips, however, the external addition of the heatsink creates thermal barriers at the epoxy and heatsink interconnections. These thermal barriers make the addition of an external heatsink less effective when used with relatively high power/high heat chips. Heat generated by the chip must be conducted through the internal alumina substrate to the external heatsink before it can be convected away. In this context alumina has certain disadvantages with regard to its thermal conductivity and thermal coefficient of expansion. Alumina has poor thermal conductivity which makes it a poor material for efficient heat transfer. Also alumina's coefficient of thermal expansion is not closely matched to silicon. The mismatch between expansion coefficients creates significant mechanical stresses between the silicon chip and the alumina substrate often causing defects within the chip.
In an endeavor to extend the performance limits of the type of heatsink/internal substrate configuration described, a number of alternative materials with better heat transfer properties have been proposed, such as aluminum nitride and beryllium oxide. These alternatives, however, generally have their own disadvantages. For example, aluminum nitride is expensive, and there are potential health hazards associated with beryllium compounds.
If the chip is to be mounted in combination with a number of other chips and further components, it may undergo a number of further mounting steps. For example, a packaging arrangement has been described in "A Systems Approach to the Evaluation of Packaging Design Alternatives", Sikorski, Kruger, and Field, International Journal of Hybrid Microelectronics, Vol. 12 No. 2, p. 102-110 (June 1989), in which the chip is mounted on an alumina leaded ceramic chip carrier (LCCC) which is thermally attached to an alumina printed wiring network (PWN) or printed circuit board (PCB) by a thermal pad of tin-lead solder, the PWN being in turn similarly soldered to a Cu/Mo/Cu carrier plate which is finally coupled to an aluminum chassis heatsink by a layer of thermal grease.
Manufacturing costs are also a major concern in designing chip mountings and packages. The conventional chip mounting and packaging techniques involve a considerable number of process and testing steps to weed out defective chips. These process and testing steps result in increased costs. The large number of steps also pose difficulties in trading off cost against effectiveness. For example, chips being mounted and encapsulated in the conventional manner, as previously described, are probe tested on the wafer, then mounted on the alumina carrier and encapsulated and tested again, then "burned in" (run for typically 24 hours at elevated temperature) and retested. This testing procedure involves several testing steps and tests the chips under abnormal conditions (without heat dissipating means attached).